dsPIC30F
TABLE 10-6:
ROTATE/SHIFT INSTRUCTIONS
Assembly
ASR
ASR
ASR
ASR
LSR
LSR
LSR
LSR
RLC
RLC
RLNC
RLNC
RRC
RRC
RRNC
RRNC
SL
SL
SL
SL
Syntax
f {,WREG}
Ws,Wd
Wb,#lit4,Wnd
Wb,Wns,Wnd
f {,WREG}
Ws,Wd
Wb,#lit4,Wnd
Wb,Wns,Wnd
f {,WREG}
Ws,Wd
f {,WREG}
Ws,Wd
f {,WREG}
Ws,Wd
f {,WREG}
Ws,Wd
f {,WREG}
Ws,Wd
Wb,#lit4,Wnd
Wb,Wns,Wnd
Description
Destination = arithmetic right shift f
Wd = arithmetic right shift Ws
Wnd = arithmetic right shift Wb by lit4
Wnd = arithmetic right shift Wb by Wns
Destination = logical right shift f
Wd = logical right shift Ws
Wnd = logical right shift Wb by lit4
Wnd = logical right shift Wb by Wns
Destination = rotate left through Carry f
Wd = rotate left through Carry Ws
Destination = rotate left (no Carry) f
Wd = rotate left (no Carry) Ws
Destination = rotate right through Carry f
Wd = rotate right through Carry Ws
Destination = rotate right (no Carry) f
Wd = rotate right (no Carry) Ws
Destination = left shift f
Wd = left shift Ws
Wnd = left shift Wb by lit4
Wnd = left shift Wb by Wns
Words
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note:
When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When
{,WREG} is not specified, the destination of the instruction is the file register f.
TABLE 10-7:
BIT INSTRUCTIONS
Assembly
BCLR
BCLR
BSET
BSET
BSW.C
BSW.Z
BTG
BTG
BTST
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
BTSTS.C
BTSTS.Z
FBCL
FF1L
FF1R
Syntax
f,#bit4
Ws,#bit4
f,#bit4
Ws,#bit4
Ws,Wb
Ws,Wb
f,#bit4
Ws,#bit4
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
Ws,Wb
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wnd
Ws,Wnd
Ws,Wnd
Description
Bit clear f
Bit clear Ws
Bit set f
Bit set Ws
Write C bit to Ws<Wb>
Write SZ bit to Ws<Wb>
Bit toggle f
Bit toggle Ws
Bit test f
Bit test Ws to C
Bit test Ws to SZ
Bit test Ws<Wb> to C
Bit test Ws<Wb> to SZ
Bit test f then set f
Bit test Ws to C then set Ws
Bit test Ws to SZ then set Ws
Find bit change from left (MSb) side
Find first one from left (MSb) side
Find first one from right (LSb) side
Words
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note:
Bit positions are specified by bit4 (0:15) for word operations.
? 2005 Microchip Technology Inc.
DS70043F-page 39
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